The present invention generally relates to semiconductor memory devices and more particularly to a semiconductor memory device having an improved access time.
In semiconductor memory devices, delay at the time of reading or writing data is caused by various reasons. Among others, contribution of peripheral circuits occupies a significant part. It should be noted that the delay caused by the peripheral circuits is much larger than the delay caused by the memory cell itself. Such peripheral circuits include sense circuits and decoders.
FIG. 1 shows a construction of a typical conventional semiconductor memory device.
Referring to FIG. 1, semiconductor memory device comprises a memory cell array 1 including a number of memory cells 1a arranged in a row and column formation, a row decoder 2 connected to word lines WL for addressing a memory cell 1a connected to one of the word lines in response to an address signal ADDRESS1 supplied thereto, a column decoder 3 acting also as a sense circuit as well as a write circuit, connected to bit lines for addressing a memory cell 1a connected to a pair of addressed bit lines BL and BL in response to another address signal ADDRESS2. Further, an output buffer circuit 4a and a read write control circuit 4b are provided for reading data from the addressed memory cell and writing data to the addressed memory cell respectively.
FIG. 2 shows a construction of the circuit 3 in detail. Only the part of the circuit 3 which is used for reading the data is illustrated. Referring to FIG. 2, a number of sense amplifiers 11-14, each comprising a transistor 5 and a transistor 6, are connected to corresponding pairs of bit lines BL1 and BL1, BL2 and BL2, BL3 and BL3, and BL4 and BL4 and so on. Further, there are provided a common data bus pair 8 and 9 wherein the data bus 8 is connected commonly to the collector of the transistor 5 forming the sense amplifiers 11-14 and the data bus 9 is connected commonly to the collector of the transistor 6 also forming the sense amplifiers 11-14. The buses 8 and 9 are connected to the output buffer circuit 4a which is a sense amplifier for detecting the difference in the current flowing through the buses 8 and 9. In response to the detected difference, the output buffer circuit 4a produces a data signal at an output terminal D.sub.OUT.
FIG. 3 shows a construction of the output buffer circuit 4a used for detecting the difference in the current between the bus 8 and the bus 9. As can be seen from FIG. 3, the output buffer circuit 4a comprises a differential amplifier 4a, having a well known construction and produces a high level output at the output terminal D.sub.OUT when the voltage level on the bus 8 is higher than that on the bus 9. Otherwise, the amplifier 4a' produces a low level output at the output terminal D.sub.OUT. As the construction and operation of such a differential amplifier is well known, further description thereof will be omitted.
Each of the sense amplifiers 11-14 includes the transistor 5 and the transistor 6 wherein the transistor 5 having the collector connected to the bus 8 has a base connected to the bit line BL and an emitter connected, commonly to the emitter of the transistor 6, to a current source 7. Similarly, the transistor 6 having the collector connected to the bus 9 has a base connected to the bit line BL and an emitter connected, commonly to the emitter of the transistor 5, to the current source 7. The current source 7 is selectively turned on in response to a column select signal which is produced by decoding the address signal ADDRESS2 by a decoding unit 3a shown in FIG. 4.
FIG. 4 shows the construction of the current source 7 in more detail. Referring to FIG. 4, the current source 7 comprises a field effect transistor connecting the emitters of the transistors 5 and 6 to the ground. The transistor 7 has a gate to which the column select signal produced by the decoding unit 3a is supplied and the transistor 7 is turned off and turned on in response to the address data ADDRESS2 supplied to the decoding unit 3a.
Thus, when the sense amplifier 1 is selected in response to the turning on of the current source 7, a current may be caused to flow either from the bus 8 to the current source 7 through the transistor 5 or from the bus 9 to the current source 7 through the transistor 6 depending on the content of information stored in the selected memory cell 1a. Thus, when there is a high level state in the bit line BL1, a current is caused to flow from the bus 8 to the current source 7 through the collector and emitter of the transistor 5. In correspondence to the high level state in the bit line BL1, a low level state appears in the bit line BL, and flow of the current through the transistor 6 is prohibited. Thus, there appears an inequality in the current flowing through the bus 8 and the bus 9, and this inequality of the current is detected by the sense amplifier 4a. When the high level state is on the bit line BL and the low level state on the bit line BL, on the other hand, a reversed situation appears such that the current flows from the bus 9 to the current source 7 through the transistor 6 while flowing of the current through the transistor 5 is prohibited.
Although such a so-called "collector dot" construction of the memory device is effective in reducing the delay of the decoding circuit, there still remains a problem in that the response of the memory device is not satisfactorily fast.
FIG. 5 explains the reason why a satisfactorily quick response cannot be obtained in the foregoing construction. Referring to FIG. 5 showing the cross-sectional view of a transistor used for the transistors 5 and 6, the transistor has an n.sup.+ -type buried collector layer 22 provided on a p-type substrate 21, and an n-type collector layer 23, p-type base layer 24 and an n-type emitter layer 25 are provided on the buried collector layer 22. Further, it will be seen that the transistors are isolated from each other by an isolation structure 26 forming a p-n junction. Although such transistors are easy to fabricate with reduced number of fabrication steps, there is a problem that a large capacitance appears at the boundary between the substrate 21 and the buried collector layer 22 forming a p-n junction and at the boundary between the collector layer 23 and the base layer 24 also forming a p-n junction. It should be noted that junction between the substrate 21 and the collector layer 22 or the junction between the collector layer 23 and the base layer 24 has a substantial area. Because of this, there appears a substantial capacitance such as C.sub.sub or C.sub.CB at the collector of the transistors 5 and 6. Such a capacitance at the collector of the transistors 5 and 6 connected to the buses 8 and 9 inevitably causes a delay at the time of reading the data and the access characteristic of the memory device is deteriorated.
It should be noted that these parasitic capacitance connected parallel with each other to the bus 8 or 9 can cause a significant delay at the time of operation of the memory device.
Such a parasitic capacitance may be reduced by using the isolation structure formed of grooves as shown in FIG. 6. Referring to FIG. 6, there are provided isolation grooves 26, in place of the isolation structure 26 of junction type of FIG. 5. Other parts are identical to the structure of FIG. 5 and further description of the device of FIG. 6 will be omitted. It should be noted that the area of the p-n junction formed along the interface between the collector layer 23 or the buried collector layer 22 and the substrate 21 is substantially reduced by replacing the p-type region 26 by the groove 26'. However, such an isolation structure using the groove is disadvantageous from the viewpoint of yield and fabrication cost.